Teoria układów logicznych - strona 2

Resolve unsolvable SST

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Resolve unsolvable SST Resolving unsolvable SST is done by splitting SST into parts, that don't contain contradictory states. In the places of division, one or several additional elements have to be switched-on and off, to differ parts containing contradictory states. If partitioning is done well...

Realizacja struktury

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Structure realization Program generates following structures: • Multiplexer, • Multiplexer with gates: o NAND gates only, o NOR gates only, o AND and OR and NOT gates, • Demultiplexer, • Tree of Multiplexers, • Multiplexer - demultiplexer. The structure is chosen by a user. The menu item w...

Synteza układu kombinacyjnego przełączania

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Syntthesiis off a combiinattiionall swiittchiing ciircuiitt The aim of a synthesis of a combinational circuit is to obtain the output functions and then a logical diagram of the circuit when given its algorithm of work. The output functions of the circuit may be i n different forms but they should ...

Komparator binarny

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Comparison If we use binary comparator for numbers in sign magnitude, 1's or 2's complement representation, the result isn't correct. It is caused by sign bit, which is equal 1 for negative numbers but in binary numbers has the biggest weight. To obtain correct result the negative numbers should ...

Konwersja z dziesiętnego na inne systemy liczbowe

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Converti ng from decimal to other number systems One of the methods used to convert from decimal to other number system is repeated radix division technique for integers and multiplication technique for fractions. During conversion process we must first break number into integer and fraction part...

Edge triggered flip flops

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Edge triggered flip flops An edge-triggered flip-flop is a device designed to respond to a raising or a falling edge of the clock signal. The influence of external signals on inputs and changes on outputs of edge-triggered flip-flops are made on the same edge of the clock. Changes of input signal...

Ogrodzony kompleks zatrzaski

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Gated latches The example of gated SR NOR-based latch is given in the Fig.6. When the control input signal C (called clock signal) is 0, signals applied to the S and R inputs can not effect the cross-coupled NOR latch circuit. However, when the clock signal C is 1, signals applied to the S and R ...

Realizacja dla typu 0

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Implementing for Type 0 A type 0 MUX design require no signal in the truth table representing the function to be partitioned off. This means, that all signals are applied to the select inputs. Also the characteristic numbers of the function are applied to the data inputs. For the specified functi...

Realizacja dla typu 1

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Implementing for Type 1. A type 1 MUX design requires one signal to be partitioned off. Continuing with the same function F, the truth table is now drawn and partitioned as shown in Fig. 10.The select inputs are independent signals a,b,c, and the data inputs are the values (the subfunctions) in t...

Realizacja dla typu 2 i 3

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
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Implementing for Type 2 and 3. Fig. 12a and b illustrate truth table partitioning for a type 2 and 3 Multiplexer design respectively. The two signals c and d are partitioned off for a type 2 MUX design, while the three signals b, c, and d are partitioned off for a type 3 MUX design. Fig. 13 a and...