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Gated latches The example of gated SR NOR-based latch is given in the Fig.6. When the control input signal C
(called clock signal) is 0, signals applied to the S and R inputs can not effect the cross-coupled
NOR latch circuit. However, when the clock signal C is 1, signals applied to the S and R inputs
can effect the cross-coupled NOR latch circuit.
The logic symbol of the gated SR latch is provided in Fig. 8.
A gated SR latch can converted to a gated D latch by simple addition of an Inverter as shown in
Fig. 9
The Inverter in the gated D latch serves two different purposes. It provides a latch circuit with only
one input (not including the clock) called data input. It also insures that SR latch inputs are always
complemented so that the signal conditions SR = 11 cannot occur. All gated latches have got the
property of transparency. The transparency property simply means that the outputs respond to an
input signal change when the control input signal is 1. For gated D latch, the data input signal D is
transferred to the Q output when control input signal is 1. The output Q signal follows the data
input signal D as long as the control input remains a logic 1. Logic symbol of the gated D latch is
given in Fig. 10.
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