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Master slave flip flops A master-slave flip-flop is designed to interrupt the logic connection between the inputs and the
outputs during the time the input control signal is a logic 1. Removing the logic connection
between the input and output signals afforded by the master-slave design provides the following
benefits: it removes the transparency property and hence race condition in feedback applications
as well as it provides a memory device, which can be used in synchronous sequential designs.
The circuit diagram of the master-slave JK flip-flop shown in Fig. 11. presents how the
transparency property is removed by interrupting signal path from the inputs to the outputs.
The master-slave JK flip-flop is simply two gated SR latches connected in cascade such that
master drives the slave. The present state outputs of the slave are fed back to the inputs of the
master such that the J inputs is qualified by ~QC while K is qualified by QC, providing steering
and thus allowing the toggle property. When the external control input signal is a logic 1, the
master is transparent from its inputs to its outputs. Because of the Inverter, during this same time
period the slave remains stable and cannot cause the race conditions through the slave via the
outputs of the master. In effect this interrupts the logic connection between the inputs and the
outputs of the device during the time the clock C is a logic 1. When the clock makes a transition
from a logic 1 to a logic 0, the data present at the J and K inputs are captured, the master is
disabled, and the slave is enabled. Changes at the master's inputs are of no consequence at this
time since it is now disabled and its outputs are stable. The slave is now transparent but the
master is supplying it with stable inputs. Master-slave can toggle only once for each external clock
signal pulse. Because master-slave utilizes both edges of the external signal applied to clock
input, this type of flip-flop is a pulse-triggered one.
Despite of the interrupt in logic connection between master and slave, this type of flip-flops can
have drawbacks. The main drawback is 1s catching or 0s catching property. This property is due
to the fact that that the master is transparent during the time the external clock is a logic one.
Therefore when the slave's output is a logic 0 and J input changes to 1 after rising edge of C, then
master will catch this set condition. The set condition is then passed on to the slave on the falling
edge of C. The slave's output becomes a logic 1, although on rising edge of the clock J input was
inactive. It means that such flip-flop catches 1s. The 0s catching is essentially the same, with the
(…)
… reset condition is caught by master and then passed on to the
slave resetting its output. The 1s catching and 0s catching property exists for all master-slave flipflops
that do not contain data-lockout feature. When data-lockout feature is present, then the input
conditions are checked only on raising edge and 1s or 0s catching does not take place. The logic
symbol of JK flip-flop with 1s and 0s…
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