Dr inż. Piotr Czekalski - strona 3

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Edge triggered flip flops

  • Politechnika Śląska
  • Teoria układów logicznych
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Edge triggered flip flops An edge-triggered flip-flop is a device designed to respond to a raising or a falling edge of the clock signal. The influence of external signals on inputs and changes on outputs of edge-triggered flip-flops are made on the same edge of the clock. Changes of input signal...

Ogrodzony kompleks zatrzaski

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  • Teoria układów logicznych
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Gated latches The example of gated SR NOR-based latch is given in the Fig.6. When the control input signal C (called clock signal) is 0, signals applied to the S and R inputs can not effect the cross-coupled NOR latch circuit. However, when the clock signal C is 1, signals applied to the S and R ...

Metoda Huffmansa

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  • Theory of Logic Circuits
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Huffman's Method 1. Obtain the primitive flow map of the circuit 2. Reduce equivalent and pseudo-equivalent states and obtain the primitive flow map without redundant states 3. Merge rows of the primitive flow map without redundant states (The m...

Realizacja dla typu 0

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  • Teoria układów logicznych
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Implementing for Type 0 A type 0 MUX design require no signal in the truth table representing the function to be partitioned off. This means, that all signals are applied to the select inputs. Also the characteristic numbers of the function are applied to the data inputs. For the specified functi...

Realizacja dla typu 1

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  • Teoria układów logicznych
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Implementing for Type 1. A type 1 MUX design requires one signal to be partitioned off. Continuing with the same function F, the truth table is now drawn and partitioned as shown in Fig. 10.The select inputs are independent signals a,b,c, and the data inputs are the values (the subfunctions) in t...

Realizacja dla typu 2 i 3

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  • Teoria układów logicznych
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Implementing for Type 2 and 3. Fig. 12a and b illustrate truth table partitioning for a type 2 and 3 Multiplexer design respectively. The two signals c and d are partitioned off for a type 2 MUX design, while the three signals b, c, and d are partitioned off for a type 3 MUX design. Fig. 13 a and...

Funkcje wykonawcze Logic. Korzystanie demultiplekserów MSI

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  • Teoria układów logicznych
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Implementing Logic Functions Using MSI Demultiplexers Since Demultiplexers do not suffer from a lack of outputs like Multiplexers do, Demultiplexer implementations are normally carried out for Boolean functions with multiple outputs. Using a Demultiplexer with n select inputs with an external OR ...

Implementing Logic Functions Using MSI Multiplexers

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  • Teoria układów logicznych
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Implementing Logic Functions Using MSI Multiplexers When a Multiplexer is used to implement a logic function, that function does not need to be minimized in the normal manner; however, a minimized function consisting of only a single literal or a single product term would be more cost-effective u...

Master slave flip flops

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  • Teoria układów logicznych
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Master slave flip flops A master-slave flip-flop is designed to interrupt the logic connection between the inputs and the outputs during the time the input control signal is a logic 1. Removing the logic connection between the input and output signals afforded by the master-slave design provides ...

Microprogrammable circuits

  • Politechnika Śląska
  • Teoria układów logicznych
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Microprogrammable circuits Microprogrammable circuits are synchronous sequential logic circuits. Their operation is defined by the memory contents, called microprogram. Therefore they are more universal comparing to hard-wired logic circuits. Mic...