Obudowa mikrokontrolerów - wykład

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Fragment notatki:

• High performance, low power AVR® 8-bit Microcontroller
• Advanced RISC architecture

– 135 powerful instructions – most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 16MIPS throughput at 16MHz
– On-chip 2-cycle multiplier
Non-volatile program and data memories
– 64/128Kbytes of in-system self-programmable flash
• Endurance: 100,000 write/erase cycles
– Optional Boot Code section with independent lock bits
• USB boot loader programmed by default in the factory
• In-system programming by on-chip boot program hardware activated after
• True read-while-write operation
• All supplied parts are pre-programed with a default USB bootloader
– 2K/4K (64K/128K flash version) bytes EEPROM
• Endurance: 100,000 write/erase cycles
– 4K/8K (64K/128K flash version) bytes internal SRAM
– Up to 64Kbytes optional external memory space
– Programming lock for software security
JTAG (IEEE std. 1149.1 compliant) interface
– Boundary-scan capabilities according to the JTAG standard
– Extensive on-chip debug support
– Programming of flash, EEPROM, fuses, and lock bits through the JTAG interface
USB 2.0 full-speed/low-speed device and on-the-go module
– Complies fully with:
– Universal serial bus specification REV 2.0
– On-the-go supplement to the USB 2.0 specification rev 1.0
– Supports data transfer rates up to 12Mbit/s and 1.5Mbit/s
USB full-speed/low speed device module with interrupt on transfer completion
– Endpoint 0 for control transfers: up to 64-bytes
– Six programmable endpoints with in or out directions and with bulk, interrupt or
isochronous transfers
– Configurable endpoints size up to 256bytes in double bank mode
– Fully independent 832bytes USB DPRAM for endpoint memory allocation
– Suspend/resume interrupts
– Power-on reset and USB bus reset
– 48MHz PLL for full-speed bus operation
– USB bus disconnection on microcontroller request
USB OTG reduced host:
– Supports host negotiation protocol (HNP) and session request protocol (SRP) for
OTG dual-role devices
– Provide status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
Peripheral features
– Two 8-bit timer/counters with separate prescaler and compare mode
– Two16-bit timer/counter with separate prescaler, compare- and capture mode
8-bit Atmel
of ISP Flash
and USB

– Real time counter with separate oscillator
– Four 8-bit PWM channels
– Six PWM channels with programmable resolution from 2 to 16 bits
– Output compare modulator
– 8-channels, 10-bit ADC
– Programmable serial USART
– Master/slave SPI serial interface
– Byte oriented 2-wire serial interface
– Programmable watchdog timer with separate on-chip oscillator
– On-chip analog comparator
– Interrupt and wake-up on pin change
Special microcontroller features
– Power-on ... zobacz całą notatkę

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