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Instruction Set Nomenclature
Status Register (SREG)
Two’s complement overflow indicator
N ⊕ V, For signed tests
Half Carry Flag
Transfer bit used by BLD and BST instructions
Global Interrupt Enable/Disable Flag
Registers and Operands
Destination (and source) register in the Register File
Source register in the Register File
Result after instruction is executed
Bit in the Register File or I/O Register (3-bit)
Bit in the Status Register (3-bit)
Indirect Address Register
(X=R27:R26, Y=R29:R28 and Z=R31:R30)
I/O location address
Displacement for direct addressing (6-bit)
RAMPX, RAMPY, RAMPZ
Registers concatenated with the X-, Y-, and Z-registers enabling indirect addressing of the whole data space on MCUs with
more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.
Register concatenated with the Z-register enabling direct addressing of the whole data space on MCUs with more than 64K
bytes data space.
Register concatenated with the Z-register enabling indirect jump and call to the whole program space on MCUs with more
than 64K words (128K bytes) program space.
STACK: Stack for return address and pushed registers
Stack Pointer to STACK
Flag affected by instruction
Flag cleared by instruction
Flag set by instruction
Flag not affected by instruction
AVR Instruction Set
AVR Instruction Set
The Program and Data Addressing Modes
The AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Program
memory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This section describes
the various addressing modes supported by the AVR architecture. In the following figures, OP means the operation code
part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, the
abstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space,
Not all addressing modes are present in all devices. Refer to the device spesific instruction summary.
Register Direct, Single Register Rd
Figure 1. Direct Single Register Addressing
The operand is contained in register d (Rd).
Register Direct, Two Registers Rd and Rr
Figure 2. Direct Register Addressing, Two Registers
Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).
Figure 3. I/O Direct Addressing
Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.
Some complex AVR Microcontrollers have more peripheral units than can be supported
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