Dr inż. Piotr Czekalski - strona 5

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Wykrywanie przepełnienia

  • Politechnika Śląska
  • Teoria układów logicznych
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Overflow detection Overflow is the most important problem that can occur during addition. Example (2's complement representation): Let (A)2=(010011.011)2 then (-A)2=(101100.101)2 One of the possible solutions of detecting overflow is based on testing the carry onto and from sign digit. If both...

Proces projektowania synchroniczny

  • Politechnika Śląska
  • Teoria układów logicznych
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Synchronous design process Typical synchronous design process can fit into 6 main steps: • Organize design specification, typically into state diagram, PS/NS table, ASM chart or timing diagram. • Perform state reduction to achieve fewer flip-flops. • Determine minimum number of flip-flops and a...

The Table of Switching Sequence method

  • Politechnika Śląska
  • Teoria układów logicznych
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The Table of Switching Sequence method (SST) (Also known as Table of Successive Connections) The Table of Switching Sequence method, also known as Table of Successive Connections is applicable for asynchronous sequential systems, given by description, time diagram or flow chart. Several steps mu...

Arithmetic operations

  • Politechnika Śląska
  • Theory of Logic Circuits
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Arithmetic operations The operations of addition, subtraction, multiplication, and division can be carried out in exactly the same manner with binary numbers as they are with decimal numbers. When number is in 1's or 2's complement representation, computer needs to use only Adder circuit and Com...

Asynchronous flipflops

  • Politechnika Śląska
  • Theory of Logic Circuits
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Asynchronous flip-flops In practice only sr flip-flops (and their modifications, like: ~s~r flip-flops) are built as asynchronous devices1. First let us consider sr basic latch implemented with the use of two NOR gates The logical symbol of this bistable device is given in the Fig.2. Numbers asso...

Iteracyjny obwody przełączania

  • Politechnika Śląska
  • Teoria układów logicznych
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Iterative switching circuits Iterative circuits are such combinational circuits that consist of a set of identical cells connected in a cascade, as shown in the picture below. In designing iterative networks we design a typical cell such as n-cell and than we are able to use it as many times as ...

Learn by example

  • Politechnika Śląska
  • Teoria układów logicznych
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Learn by example 1's components and 0's factors, as shown on Fig. 2, are giving output function F based on 20 input signals X1...X20 . First, let's analyze first 1's component. Each single-variable literal is covered by some element of 0's factor set, so we analyze all possible arrangements for...

Krótki przegląd

  • Politechnika Śląska
  • Teoria układów logicznych
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Short overview Program MuxDmux enables computer assisted design for realizations of circuits with multiplexers and demultiplexers. The operation of the program consists of entering a function definition and then selecting a structure in which this function will be implemented. Function may be en...

Systemy pozycyjne ważona liczba

  • Politechnika Śląska
  • Teoria układów logicznych
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Weighted positional number systems In weighted-positional number systems each number is represented by sequence of digits followed by a comma or period (which depends on country). The value of a particular digit in this number depends on its position in the sequence of digits relative to a radix ...

Algorithms for system synthesis and optimization

  • Politechnika Śląska
  • Theory of Logic Circuits
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Algorithms for system synthesis and optimization There are many CAD methods helping Circuit developer do their job faster and better. During this labs you will test two methods: 1. A Table of Switching Sequence method for synthesis of sequential...