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Realizacja dla typu 1

  • Politechnika Śląska
  • Teoria układów logicznych
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Implementing for Type 1. A type 1 MUX design requires one signal to be partitioned off. Continuing with the same function F, the truth table is now drawn and partitioned as shown in Fig. 10.The select inputs are independent signals a,b,c, and the data inputs are the values (the subfunctions) in t...

Realizacja dla typu 2 i 3

  • Politechnika Śląska
  • Teoria układów logicznych
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Implementing for Type 2 and 3. Fig. 12a and b illustrate truth table partitioning for a type 2 and 3 Multiplexer design respectively. The two signals c and d are partitioned off for a type 2 MUX design, while the three signals b, c, and d are partitioned off for a type 3 MUX design. Fig. 13 a and...

Funkcje wykonawcze Logic. Korzystanie demultiplekserów MSI

  • Politechnika Śląska
  • Teoria układów logicznych
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Implementing Logic Functions Using MSI Demultiplexers Since Demultiplexers do not suffer from a lack of outputs like Multiplexers do, Demultiplexer implementations are normally carried out for Boolean functions with multiple outputs. Using a Demultiplexer with n select inputs with an external OR ...

Implementing Logic Functions Using MSI Multiplexers

  • Politechnika Śląska
  • Teoria układów logicznych
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Implementing Logic Functions Using MSI Multiplexers When a Multiplexer is used to implement a logic function, that function does not need to be minimized in the normal manner; however, a minimized function consisting of only a single literal or a single product term would be more cost-effective u...

Master slave flip flops

  • Politechnika Śląska
  • Teoria układów logicznych
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Master slave flip flops A master-slave flip-flop is designed to interrupt the logic connection between the inputs and the outputs during the time the input control signal is a logic 1. Removing the logic connection between the input and output signals afforded by the master-slave design provides ...

Microprogrammable circuits

  • Politechnika Śląska
  • Teoria układów logicznych
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Microprogrammable circuits Microprogrammable circuits are synchronous sequential logic circuits. Their operation is defined by the memory contents, called microprogram. Therefore they are more universal comparing to hard-wired logic circuits. Mic...

Moore and Mealy Type Synchronous State Machines

  • Politechnika Śląska
  • Teoria układów logicznych
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Moore and Mealy Type Synchronous State Machines Synchronous state machine is the one, where its internal state changes along with synchronous input C (clock) or CLK. Typically C has rectangle waveform. State usually changes on arising or falling edge of clock signal (Edge-Triggered Devices). Syn...

Number representations

  • Politechnika Śląska
  • Teoria układów logicznych
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Number representations So far only positive numbers were presented. As in decimal, also in other systems we have to present both positive (represented with “+” sign) and negative (represented with “-“ sign) values. This notation is called sign magnitude. Computers are generally not designed to in...

Opcje i elementy menu

  • Politechnika Śląska
  • Teoria układów logicznych
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Options and menu items Allows user to change working behavior and result presentation of software: - Diagram options, MENU: [Options/Diagram] - Working (partially / only end solution) , MENU: [Options/Working], when partially is selected, system prompts user after each step during solution (in c...