Politechnika Śląska - strona 151

Memmove

  • Politechnika Śląska
  • dr inż. Piotr Fabian
  • Fundamentals of Computer Programming
Pobrań: 0
Wyświetleń: 924

Memmove  void *memmove(void *dest, const void *src, size_t n);  Copies a block of n bytes from src to dest  Even when the src and dest blocks overlap, bytes in the overlapping locations are copied correctly #include #include int main() { char dest[] = "abcdefghijklmnopqrstuvwxyz0123456789...

Asynchronous counters

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Theory of Logic Circuits
Pobrań: 0
Wyświetleń: 784

Asynchronous counters In asynchronous counters the control inputs of flip-flops are not driven by the same signal source. The common element used in a design of such a counter is a simplified symbol of a flip-flop. By such symbol we understand any flip-flop working as a frequency divider by 2. I...

Asynchronous sequential logic circuits

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Theory of Logic Circuits
Pobrań: 7
Wyświetleń: 812

Asynchronous sequential logic circuits All switching circuits belong to one of two classes: combinational or sequential. On contrary to combinational logic circuits, the operation of sequential ones is dependent not only on the present state of external inputs, but also on the state of these inpu...

Binary adders

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Theory of Logic Circuits
Pobrań: 0
Wyświetleń: 749

Bi nary adders Binary adder is a basic circuit performing addition operation for binary numbers A and B. This simple combinational circuit obtains two signals Si (sum) and Ci+1 (carry to next position) from signals Ai, Bi and Ci (carry from previous position). Fig. 1 presents the truth table and ...

Komparator binarny

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
Pobrań: 0
Wyświetleń: 1610

Comparison If we use binary comparator for numbers in sign magnitude, 1's or 2's complement representation, the result isn't correct. It is caused by sign bit, which is equal 1 for negative numbers but in binary numbers has the biggest weight. To obtain correct result the negative numbers should ...

Konwersja z dziesiętnego na inne systemy liczbowe

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
Pobrań: 0
Wyświetleń: 595

Converti ng from decimal to other number systems One of the methods used to convert from decimal to other number system is repeated radix division technique for integers and multiplication technique for fractions. During conversion process we must first break number into integer and fraction part...

Edge triggered flip flops

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
Pobrań: 0
Wyświetleń: 721

Edge triggered flip flops An edge-triggered flip-flop is a device designed to respond to a raising or a falling edge of the clock signal. The influence of external signals on inputs and changes on outputs of edge-triggered flip-flops are made on the same edge of the clock. Changes of input signal...

Ogrodzony kompleks zatrzaski

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
Pobrań: 0
Wyświetleń: 889

Gated latches The example of gated SR NOR-based latch is given in the Fig.6. When the control input signal C (called clock signal) is 0, signals applied to the S and R inputs can not effect the cross-coupled NOR latch circuit. However, when the clock signal C is 1, signals applied to the S and R ...

Metoda Huffmansa

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Theory of Logic Circuits
Pobrań: 0
Wyświetleń: 847

Huffman's Method 1. Obtain the primitive flow map of the circuit 2. Reduce equivalent and pseudo-equivalent states and obtain the primitive flow map without redundant states 3. Merge rows of the primitive flow map without redundant states (The m...

Realizacja dla typu 0

  • Politechnika Śląska
  • dr inż. Piotr Czekalski
  • Teoria układów logicznych
Pobrań: 0
Wyświetleń: 595

Implementing for Type 0 A type 0 MUX design require no signal in the truth table representing the function to be partitioned off. This means, that all signals are applied to the select inputs. Also the characteristic numbers of the function are applied to the data inputs. For the specified functi...